Enterprise Solutions News

New HGST SSDs to Help Expedite Big Data Analytics

Says HGST FlashMAX PCIe SSDs The SSD demonstration utilizes a PCIe interface and delivers three million random read IOs per second of 512 Bytes each

Enterprise storage vendor HGST, a Western Digital company, is previewing a new architecture for solid-state drives (SSDs) that enables applications to provide faster insights to the data-intensive questions of tomorrow.

The demonstration shows unprecedented SSD performance levels that are achieved by utilizing a combination of HGST’s new, latency-optimized interface protocols with next-generation non-volatile memory components announced the press release.

The SSD demonstration utilizes a PCIe interface and delivers three million random read IOs per second of 512 Bytes each when operating in a queued environment and a random read access latency of 1.5 microseconds (us) in non-queued settings, delivering results that cannot be achieved with existing SSD architectures and NAND Flash memories. This performance is orders of magnitude faster than existing Flash based SSDs, resulting in a new class of block storage devices.

“The PCM SSD demonstration is a great example for how HGST sets the pace of the rapidly evolving storage industry,” said Steve Campbell, chief technology officer, HGST. “This technology is the result of several years of research and advanced development aimed at delivering new levels of acceleration for enterprise applications. The combination of HGST’s low-latency interface protocol and next-generation non-volatile memories delivers unprecedented performance, and creates exciting opportunities for new software and system architectures that HGST is exploring with our customers and industry partners.”

“Three million IOPs is exceptional, but that is not the most exciting part of the demonstration,” said Dr. Zvonimir Bandic, manager of Storage Architecture at HGST Research. “What is really exciting is to be able to deliver latencies close to 1us for small block random reads. This is something that just cannot be done with NAND Flash and current controller and interface technologies.”

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